Dr. Thomas Schweizer

Eberhard-Karls-Universit├Ąt T├╝bingen
Wilhelm-Schickard Institut f├╝r Informatik
Lehrstuhl Technische Informatik

72076 T├╝bingen

E-Mail: tschweiz

Sprechstunde: nach Vereinbarung

Kontakt-Formular

Publikationen

 Alle Publikationen im BibTex-Format

    2016

      M├Ąrz 2016
      • T. Schweizer, M. Simsek, O. Bringmann, W. Rosenstiel
          Eine Tcl-basierte Methode zur Fehlerinjektion und Fehlereffektsimulation/-emulation auf Xilinx-FPGAs
        Proceedings Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) Workshop 2016, Freiburg, Germany
      • K. L├╝beck, D. Morgenstern, T. Schweizer, D. Peterson, W. Rosenstiel, O. Bringmann
          Neues Konzept zur Steigerung der Zuverlaessigkeit einer ARM-basierten Prozessorarchitektur unter Verwendung eines CGRAs
        Proceedings Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) Workshop 2016, Freiburg, Germany

      2015

        2015
        • W. Lange, M. Bogdan, T. Schweizer
            Eingebettete Systeme: Entwurf, Modellierung und Synthese (2. Auflage)
          De Gruyter
        2015
        • L. Bauer, J. Henkel, A. Herkersdorf, M. A. Kochte, J. M. K├╝hn, W. Rosenstiel, T. Schweizer, S. Wallentowitz, V. Wenzel, T. Wild, H.-J.Wunderlich, H. Zhang
           Adaptive multi-layer techniques for increased system dependability
          it - Information Technology, Vol.57(3), De Gruyter

        2014

          Dezember 2014
          • S. Schulz, T. Schweizer, O. Bringmann, W. Rosenstiel
             Rotated Parallel Mapping: A Novel Approach for Mapping Data Parallel Applications on CGRAs
            International Conference on ReConFigurable Computing and FPGAs (ReConFig)

          2013

            Dezember 2013
            • D. Peterson, T. Schweizer, O. Bringmann, W. Rosenstiel
               StML: Bridging the Gap between FPGA Design and HDL Circuit Description
              Proceeding of the International Conference on Field Programmable Technology (ICFPT), Kyoto, Japan
            • J.M. K├╝hn, T. Schweizer, D. Peterson, T. Kuhn, W. Rosenstiel
               Testing Reliability Techniques for SoCs with Fault Tolerant CGRA by using live FPGA Fault Injection
              Proceeding of the International Conference on Field Programmable Technology (ICFPT), Kyoto, Japan
            • T. Schweizer, L. Ferreira, M. Ritt, W. Rosenstiel
               Timing Error Handling on CGRAs
              International Conference on ReConFigurable Computing and FPGAs (ReConFig)
            April 2013
            • T. Schweizer, D. Peterson, J. M. K├╝hn, T. Kuhn, W. Rosenstiel
                A Fast and Accurate FPGA-Based Fault Injection System
              IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Seattle, USA

            2012

              Juni 2012
              • J. M. K├╝hn, S. Eisenhardt, T. Schweizer, T. Kuhn, W. Rosenstiel
                 Improving System Reliability using Dynamic Functional Verification on CGRAs
                Proceedings of the International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), Okinawa, Japan
              Mai 2012
              • T. Schweizer, A. Kuester, S. Eisenhardt, T. Kuhn, W. Rosenstiel
                 Using Run-Time Reconfiguration to Implement Fault-Tolerant Coarse Grained Reconfigurable Architectures
                International Parellel and Distributed Processing Symposium Workshops (IPDPSW), IEEE, Shanghai, China

              2011

                November 2011
                • T. Schweizer, P. Schlicker, S. Eisenhardt, T. Kuhn, W. Rosenstiel
                   Low-Cost TMR for Fault-Tolerance on Coarse-Grained Reconfigurable Architectures
                  International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, Cancun, Mexico
                Oktober 2011
                • S. Eisenhardt, A. K├╝ster, T. Schweizer, T. Kuhn, W. Rosenstiel
                   Spatial and Temporal Data Path Remapping for Fault-Tolerant Coarse-Grained Reconfigurable Architectures
                  IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Vancouver, Canada
                Juni 2011
                • S. Eisenhardt, A. K├╝ster, T. Schweizer, T. Kuhn, W. Rosenstiel
                   Runtime Datapath Remapping for Fault-Tolerant Coarse-Grained Reconfigurable Architectures
                  International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), IEEE, Montpellier, Frankreich

                2010

                  August 2010
                  • T. Schweizer, J. Oliveira, T. Kuhn, W. Rosenstiel
                     Charge Recycling in Voltage-Dithered Circuits
                    Journal of Low Power Electronics
                  Mai 2010
                  • Y. Jacobs, T. Schweizer, W. Rosenstiel
                     High Level Synthesis of the CHStone Benchmark Suite using Cadence┬« C-to-Silicon-Compiler
                    CDNLive!
                  Februar 2010
                  • S. Eisenhardt, T. Schweizer, J. Oliveira, T. Kuhn, W. Rosenstiel
                     Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications: Evaluation and Design Methods for Processor-Like Reconfigurable Architectures
                    Springer

                  2009

                    Dezember 2009
                    • S. Eisenhardt, T. Schweizer, A. Bernauer, T. Kuhn, W. Rosenstiel
                       Prevention of Hot Spot Development on Coarse-Grained Dynamically Reconfigurable Architectures
                      International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, Cancun, Mexico
                    September 2009
                    • J.Oliveira Filho, S. Masekowsky, T. Schweizer, W.Rosenstiel
                       CGADL: an Architecture Description Language for Coarse-Grained Reconfigurable Arrays
                      IEEE Transactions in Very Large Scale Integration Systems
                    • T. Schweizer, J. Oliveira, T. Kuhn, W. Rosenstiel
                       Low Energy Voltage Dithering in Dual VDD Circuits
                      Power and Timing Modeling, Optimization and Simulation, PATMOS, Delft, Netherlands
                    • T. Schweizer, J. Sommer, W. Rosenstiel
                       Verfahren und Vorrichtung zur Unterst├╝tzung von Green-IT und energieautarker Systeme DE 10 2009 039 677 B4
                      Deutsches Patent- und Markenamt
                    Publikationen ohne Monatsangabe 2009
                    • B.Sander, J. Schnerr, O. Bringmann, T. Schweizer, W. Rosenstiel
                       Schnelle, zyklengenaue Absch├Ątzung der Leistungsaufnahme eingebetteter Prozessoren auf Systemebene
                      Workshop 2009 - Electronic Design Automation (EDA)

                    2008

                      Dezember 2008
                      • S. Eisenhardt, T. Oppold, T. Schweizer, W. Rosenstiel
                         Optimizing Partial Reconfiguration of Multi-Context Architectures
                        International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, Cancun, Mexico
                      September 2008
                      • S. Eisenhardt, T. Schweizer, J. Oliveira, T. Oppold, W. Rosenstiel, A. Thomas, J. Becker, F. Hannig, D. Kissler, H. Dutta, J. Teich, H. Hinkelmann, P. Zipf, M. Glesner
                         SPP1148 Booth: Coarse-Grained Reconfiguration
                        In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), p.349, Heidelberg, Germany

                      2007

                        Oktober 2007
                        • J. O. Filho, S. Masekowsky, T. Schweizer, W. Rosenstiel
                            An Architecture Description Language for coarse-grained Reconfigurable Arrays
                          International Conference on Hardware/Software Codesign and System Synthesis (CODES) - Workshop on Application Specific Processors (WASP), Salzburg, Austria
                        Publikationen ohne Monatsangabe 2007
                        • T. Oppold, T. Schweizer, J. F. Oliveira, S. Eisenhardt, W. Rosenstiel
                             CRC - Concepts and Evaluation of Processor-Like Reconfigurable Archtitectures
                          it - Information Technology, DOI: 10. 1524/itit, 49. 3. 157, Vol.49(3)
                        • M. Rullmann, S. Siegel, R. Merker, J. O. Filho, T. Schweizer, T. Oppold, W. Rosenstiel
                            Efficient Mapping and Functional Verification of Parallel Algorithms on a Multi-Context Reconfigurable Architecture
                          20. International Conference on Architecture of Computing Systems (ARCS), Workshop on Dynamically Reconfigurable Systems (DRS), Z├╝rich, Schweiz
                        • T. Schweizer, T. Oppold, J. O. Filho, S. Eisenhardt, K. Blocher, W. Rosenstiel
                            Exploiting Slack Time in Dynamically Reconfigurable Processor Architectures
                          International Conference on Field Programmable Technology (ICFPT), Kitakyushu, Japan

                        2006

                          September 2006
                          • J. O. Filho, T. Schweizer, T. Oppold, T. Kuhn, W. Rosenstiel,
                              Tuning Coarse-Grained Reconfigurable Architectures towards an Application Domain
                            3. International Conference on Reconfigurable Computing and FPGAs (ReConfig), p.71-77, San Luis Potosi, Mexiko
                          Publikationen ohne Monatsangabe 2006
                          • T. Oppold, T. Schweizer, J. F. Oliveira, S. Eisenhardt, T. Kuhn, W. Rosenstiel
                              Execution Schemes for Dynamically Reconfigurable Architectures
                            Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), Nagoya, Japan

                          2005

                          • T. Oppold, T. Schweizer, T. Kuhn, W. Rosenstiel, U. Kanus, W. Stra├čer
                              Evaluation of Ray Casting on Processor-Like Reconfigurable Architectures
                            International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland
                          • T. Schweizer, J. F. Oliveira, T. Oppold, T. Kuhn, W. Rosenstiel
                              Evaluation of Temporal-Spatial Voltage Scaling for Processor-Like Reconfigurable Architectures
                            Euro DesignCon, Munich, Germany

                          2004

                          • T. Oppold, T. Schweizer, T. Kuhn, W. Rosenstiel
                              A Design Environment for Processor-Like Reconfigurable Hardware
                            IEEE International Conference on Parallel Computing in Electrical Engineering (PARELEC), Dresden, Germany
                          • T. Oppold, T. Schweizer, T. Kuhn, W. Rosenstiel
                              A New Design Approach for Processor-Like Reconfigurable Hardware
                            Euro DesignCon, M├╝nchen
                          • T. Oppold, T. Schweizer, T. Kuhn, W. Rosenstiel
                              Cost Functions for the Design of Dynamically Reconfigurable Processor Architectures
                            Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), Kanazawa, Japan
                          • M. Winterholer, C. Schulz-Key, T. Schweizer, T. Kuhn, W. Rosenstiel
                             Object-Oriented Hardware Synthesis with SystemC
                            In Proceedings of Forum on Design Languages (FDL)
                          • C. Schulz-Key, M. Winterholer, T. Schweizer, T. Kuhn, , W. Rosenstiel
                              Object-Oriented Modeling and Synthesis of SystemC Specifications
                            Asia South Pacific Design Automation Conference (ASPDAC), Yokohama, Japan