Dr. Sven Eisenhardt

Eberhard-Karls-Universität Tübingen
Wilhelm-Schickard Institut für Informatik
Lehrstuhl Technische Informatik

72076 Tübingen

Kontakt-Formular

Projekte

      Forschungsinteressen

      Dynamisch Rekonfigurierbare Prozessoren, SoC Kommunikation, Zuverlässigkeit und Fehlertoleranz, SystemC Modellierung

      Lehre

      • SS 2011
        Proseminar: Zuverlässige Rechensysteme
      • SS 2010
        Seminar: Automotive IT
      • WS 2009/2010
        Seminar: Automotive IT
      • WS 2008/2009
        Proseminar: Entwurf eingebetteter Systeme
      • WS 2007/2008
        Proseminar: Der Weg zum Multicore

      Publikationen

       Alle Publikationen im BibTex-Format

        2012

          Dezember 2012
          • S. Eisenhardt
              Vorausschauende Rekonfiguration dynamisch rekonfigurierbarer Prozessoren in einem System on Chip
            Dissertation Universität Tübingen
          Juni 2012
          • J. M. Kühn, S. Eisenhardt, T. Schweizer, T. Kuhn, W. Rosenstiel
             Improving System Reliability using Dynamic Functional Verification on CGRAs
            Proceedings of the International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), Okinawa, Japan
          Mai 2012
          • T. Schweizer, A. Kuester, S. Eisenhardt, T. Kuhn, W. Rosenstiel
             Using Run-Time Reconfiguration to Implement Fault-Tolerant Coarse Grained Reconfigurable Architectures
            International Parellel and Distributed Processing Symposium Workshops (IPDPSW), IEEE, Shanghai, China

          2011

            November 2011
            • T. Schweizer, P. Schlicker, S. Eisenhardt, T. Kuhn, W. Rosenstiel
               Low-Cost TMR for Fault-Tolerance on Coarse-Grained Reconfigurable Architectures
              International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, Cancun, Mexico
            Oktober 2011
            • S. Eisenhardt, A. Küster, T. Schweizer, T. Kuhn, W. Rosenstiel
               Spatial and Temporal Data Path Remapping for Fault-Tolerant Coarse-Grained Reconfigurable Architectures
              IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Vancouver, Canada
            Juni 2011
            • S. Eisenhardt, A. Küster, T. Schweizer, T. Kuhn, W. Rosenstiel
               Runtime Datapath Remapping for Fault-Tolerant Coarse-Grained Reconfigurable Architectures
              International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), IEEE, Montpellier, Frankreich

            2010

              Februar 2010
              • S. Eisenhardt, T. Schweizer, J. Oliveira, T. Kuhn, W. Rosenstiel
                 Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications: Evaluation and Design Methods for Processor-Like Reconfigurable Architectures
                Springer

              2009

                Dezember 2009
                • S. Eisenhardt, T. Schweizer, A. Bernauer, T. Kuhn, W. Rosenstiel
                   Prevention of Hot Spot Development on Coarse-Grained Dynamically Reconfigurable Architectures
                  International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, Cancun, Mexico
                März 2009
                • S. Eisenhardt, J. Oliveira, T. Kuhn, W. Rosenstiel
                   Speculative Configuration Prefetching for Multi-Context Architectures
                  Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), Okinawa, Japan

                2008

                  Dezember 2008
                  • S. Eisenhardt, T. Oppold, T. Schweizer, W. Rosenstiel
                     Optimizing Partial Reconfiguration of Multi-Context Architectures
                    International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, Cancun, Mexico
                  September 2008
                  • S. Eisenhardt, T. Schweizer, J. Oliveira, T. Oppold, W. Rosenstiel, A. Thomas, J. Becker, F. Hannig, D. Kissler, H. Dutta, J. Teich, H. Hinkelmann, P. Zipf, M. Glesner
                     SPP1148 Booth: Coarse-Grained Reconfiguration
                    In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), p.349, Heidelberg, Germany

                  2007

                  • T. Oppold, T. Schweizer, J. F. Oliveira, S. Eisenhardt, W. Rosenstiel
                       CRC - Concepts and Evaluation of Processor-Like Reconfigurable Archtitectures
                    it - Information Technology, DOI: 10. 1524/itit, 49. 3. 157, Vol.49(3)
                  • T. Schweizer, T. Oppold, J. O. Filho, S. Eisenhardt, K. Blocher, W. Rosenstiel
                      Exploiting Slack Time in Dynamically Reconfigurable Processor Architectures
                    International Conference on Field Programmable Technology (ICFPT), Kitakyushu, Japan
                  • T. Oppold, S. Eisenhardt, W. Rosenstiel
                      Optimization of Area and Performance by Processor-Like Reconfiguration
                    International Parallel and Distributed Processing Symposium (IPDPS) - Reconfigurable Architectures Workshop (RAW), Long Beach, USA

                  2006

                  • T. Oppold, S. Eisenhardt, W. Rosenstiel
                      Design and Validation of Execution Schemes for Dynamically Reconfigurable Architectures
                    International Conference on Field Programmable Technology (FPT), Bangkok, Thailand
                  • T. Oppold, T. Schweizer, J. F. Oliveira, S. Eisenhardt, T. Kuhn, W. Rosenstiel
                      Execution Schemes for Dynamically Reconfigurable Architectures
                    Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), Nagoya, Japan