Publikationen

 Alle Publikationen im BibTex-Format

    2015

      M├Ąrz 2015
      • J. K├╝hn, D. Peterson, H. Amano, O. Bringmann, W. Rosenstiel
         Spatial and Temporal Granularity Limits of Body Biasing in UTBB-FDSOI
        Design, Automation and Test in Europe (DATE), Grenoble, France

      2013

        Dezember 2013
        • D. Peterson, T. Schweizer, O. Bringmann, W. Rosenstiel
           StML: Bridging the Gap between FPGA Design and HDL Circuit Description
          Proceeding of the International Conference on Field Programmable Technology (ICFPT), Kyoto, Japan
        • J.M. K├╝hn, T. Schweizer, D. Peterson, T. Kuhn, W. Rosenstiel
           Testing Reliability Techniques for SoCs with Fault Tolerant CGRA by using live FPGA Fault Injection
          Proceeding of the International Conference on Field Programmable Technology (ICFPT), Kyoto, Japan
        • T. Schweizer, L. Ferreira, M. Ritt, W. Rosenstiel
           Timing Error Handling on CGRAs
          International Conference on ReConFigurable Computing and FPGAs (ReConFig)
        April 2013
        • T. Schweizer, D. Peterson, J. M. K├╝hn, T. Kuhn, W. Rosenstiel
            A Fast and Accurate FPGA-Based Fault Injection System
          IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Seattle, USA

        2012

          Juni 2012
          • J. M. K├╝hn, S. Eisenhardt, T. Schweizer, T. Kuhn, W. Rosenstiel
             Improving System Reliability using Dynamic Functional Verification on CGRAs
            Proceedings of the International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), Okinawa, Japan
          Mai 2012
          • T. Schweizer, A. Kuester, S. Eisenhardt, T. Kuhn, W. Rosenstiel
             Using Run-Time Reconfiguration to Implement Fault-Tolerant Coarse Grained Reconfigurable Architectures
            International Parellel and Distributed Processing Symposium Workshops (IPDPSW), IEEE, Shanghai, China

          2011

            November 2011
            • T. Schweizer, P. Schlicker, S. Eisenhardt, T. Kuhn, W. Rosenstiel
               Low-Cost TMR for Fault-Tolerance on Coarse-Grained Reconfigurable Architectures
              International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, Cancun, Mexico
            Oktober 2011
            • S. Eisenhardt, A. K├╝ster, T. Schweizer, T. Kuhn, W. Rosenstiel
               Spatial and Temporal Data Path Remapping for Fault-Tolerant Coarse-Grained Reconfigurable Architectures
              IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Vancouver, Canada
            Juni 2011
            • S. Eisenhardt, A. K├╝ster, T. Schweizer, T. Kuhn, W. Rosenstiel
               Runtime Datapath Remapping for Fault-Tolerant Coarse-Grained Reconfigurable Architectures
              International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), IEEE, Montpellier, Frankreich

            2010

              September 2010
              • A. Bernauer, J. Zeppenfeld, O. Bringmann, A. Herkersdorf, W. Rosenstiel
                   Combining software and hardware LCS for lightweight on-chip learning
                DIPES/BICC 2010, IFIP AICT 329, p.279-290, The original publication is available at http://springerlink.com/content/5h85381330886706/
              August 2010
              • T. Schweizer, J. Oliveira, T. Kuhn, W. Rosenstiel
                 Charge Recycling in Voltage-Dithered Circuits
                Journal of Low Power Electronics
              • B. Sander, A. Bernauer, W. Rosenstiel
                  Design and Run-time Reliability at the Electronic System Level
                IPSJ Transactions on System LSI Design Methodology, Vol.3, p.140-160
              Juli 2010
              • B. Rakitsch, A. Bernauer, O. Bringmann, W. Rosenstiel
                 Pruning population size in XCS for complex problems
                Proceedings World Congress on Computational Intelligence (WCCI), p.3383-3390, IEEE, Barcelona, Spain
              Mai 2010
              • Y. Jacobs, T. Schweizer, W. Rosenstiel
                 High Level Synthesis of the CHStone Benchmark Suite using Cadence┬« C-to-Silicon-Compiler
                CDNLive!

              2009

                Dezember 2009
                • S. Eisenhardt, T. Schweizer, A. Bernauer, T. Kuhn, W. Rosenstiel
                   Prevention of Hot Spot Development on Coarse-Grained Dynamically Reconfigurable Architectures
                  International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, Cancun, Mexico
                September 2009
                • J.Oliveira Filho, S. Masekowsky, T. Schweizer, W.Rosenstiel
                   CGADL: an Architecture Description Language for Coarse-Grained Reconfigurable Arrays
                  IEEE Transactions in Very Large Scale Integration Systems
                • A. Bernauer, O. Bringmann, W. Rosenstiel
                    Generic Self-Adaptation to Reduce Design Effort for System-on-Chip
                  IEEE International Conference on Self-Adaptive and Self-Organizing Systems, p.126-135, San Francisco
                • T. Schweizer, J. Oliveira, T. Kuhn, W. Rosenstiel
                   Low Energy Voltage Dithering in Dual VDD Circuits
                  Power and Timing Modeling, Optimization and Simulation, PATMOS, Delft, Netherlands
                • T. Schweizer, J. Sommer, W. Rosenstiel
                   Verfahren und Vorrichtung zur Unterst├╝tzung von Green-IT und energieautarker Systeme DE 10 2009 039 677 B4
                  Deutsches Patent- und Markenamt

                2008

                  Dezember 2008
                  • S. Eisenhardt, T. Oppold, T. Schweizer, W. Rosenstiel
                     Optimizing Partial Reconfiguration of Multi-Context Architectures
                    International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, Cancun, Mexico
                  Oktober 2008
                  • Andreas Bernauer, Dirk Fritz, Wolfgang Rosenstiel
                     Evaluation of the Learning Classifier System XCS for SoC run-time control
                    Lecture Notes in Informatics, Vol.134, p.761-768, Springer, Gesellschaft f├╝r Informatik
                  Publikationen ohne Monatsangabe 2008
                  • Andreas Bernauer, Dirk Fritz, Bj├Ârn Sander, Oliver Bringmann, Wolfgang Rosenstiel
                      Current state of ASoC design methodology
                    Organic Computing - Controlled Self-organization, Nr.08141, Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Dagstuhl, Germany, ISSN 1862-4405

                  2007

                    Oktober 2007
                    • J. O. Filho, S. Masekowsky, T. Schweizer, W. Rosenstiel
                        An Architecture Description Language for coarse-grained Reconfigurable Arrays
                      International Conference on Hardware/Software Codesign and System Synthesis (CODES) - Workshop on Application Specific Processors (WASP), Salzburg, Austria
                    Publikationen ohne Monatsangabe 2007
                    • M. Rullmann, S. Siegel, R. Merker, J. O. Filho, T. Schweizer, T. Oppold, W. Rosenstiel
                        Efficient Mapping and Functional Verification of Parallel Algorithms on a Multi-Context Reconfigurable Architecture
                      20. International Conference on Architecture of Computing Systems (ARCS), Workshop on Dynamically Reconfigurable Systems (DRS), Z├╝rich, Schweiz
                    • T. Schweizer, T. Oppold, J. O. Filho, S. Eisenhardt, K. Blocher, W. Rosenstiel
                        Exploiting Slack Time in Dynamically Reconfigurable Processor Architectures
                      International Conference on Field Programmable Technology (ICFPT), Kitakyushu, Japan

                    2006

                      Oktober 2006
                      • A. Bouajila, J. Zeppenfeld, W. Stechele, A. Herkersdorf, A. Bernauer, O. Bringmann, W. Rosenstiel
                          Organic Computing at the System on Chip Level
                        In Proceedings of the IFIP International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC), Springer
                      September 2006
                      • A. Bernauer, O. Bringmann, W. Rosenstiel, A. Bouajila, W. Stechele, A. Herkersdorf
                          An Architecture for Runtime Evaluation of SoC Reliability
                        In INFORMATIK - Informatik f├╝r Menschen, GI-Edition - Lecture Notes in Informatics, Vol.93, p.177-185, K├Âlle Verlag, Bonn
                      August 2006
                      • A. Bouajila, A. Bernauer, A. Herkersdorf, W. Rosenstiel, O. Bringmann, W. Stechele
                          Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoC
                        In Yi Pan, Franz J. Rammig, Hartmut Schmeck, and Mauricio Solar, editors, 1st IFIP International Conference on Biologically Inspired Cooperative Computing (BICC), Vol.216(107-113), Springer, Boston, MA, USA
                      Publikationen ohne Monatsangabe 2006
                      • T. Oppold, T. Schweizer, J. F. Oliveira, S. Eisenhardt, T. Kuhn, W. Rosenstiel
                          Execution Schemes for Dynamically Reconfigurable Architectures
                        Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), Nagoya, Japan
                      • A. Herkersdorf, W. Rosenstiel
                          Towards a Framework and a Design Methodology for Autonomic Integrated System
                        In Proceedings Dynamically Reconfigurable Systems Self-Organization and Emergence, Architecture of Computing Systems (ARCS), p.101-108

                      2005

                      • T. Oppold, T. Schweizer, T. Kuhn, W. Rosenstiel, U. Kanus, W. Stra├čer
                          Evaluation of Ray Casting on Processor-Like Reconfigurable Architectures
                        International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland
                      • T. Schweizer, J. F. Oliveira, T. Oppold, T. Kuhn, W. Rosenstiel
                          Evaluation of Temporal-Spatial Voltage Scaling for Processor-Like Reconfigurable Architectures
                        Euro DesignCon, Munich, Germany

                      2004

                      • T. Oppold, T. Schweizer, T. Kuhn, W. Rosenstiel
                          A Design Environment for Processor-Like Reconfigurable Hardware
                        IEEE International Conference on Parallel Computing in Electrical Engineering (PARELEC), Dresden, Germany
                      • T. Oppold, T. Schweizer, T. Kuhn, W. Rosenstiel
                          A New Design Approach for Processor-Like Reconfigurable Hardware
                        Euro DesignCon, M├╝nchen
                      • T. Oppold, T. Schweizer, T. Kuhn, W. Rosenstiel
                          Cost Functions for the Design of Dynamically Reconfigurable Processor Architectures
                        Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), Kanazawa, Japan
                      • C. Schulz-Key, M. Winterholer, T. Schweizer, T. Kuhn, , W. Rosenstiel
                          Object-Oriented Modeling and Synthesis of SystemC Specifications
                        Asia South Pacific Design Automation Conference (ASPDAC), Yokohama, Japan

                      2001

                      • T. Kuhn, T. Oppold, C. Schulz-Key, M. Winterholer, W. Rosenstiel, M. Edwards, , Y. Kashai
                          Object Oriented Hardware Synthesis and Verification
                        14. International Symposium on System Synthesis (ISSS), Montr├ęal, Qu├ębec, Kanada