Adaptive Reliability for Embedded Systems
The financial impact of reliability techniques will eventually make CMOS-based silicon scaling economically unfeasible. Therefore, low cost reliability methods are necessary to lower the overall cost in VLSI systems. Coarse-grained reconfigurable cores (CGRCs) already contain many structures that allow high reliability and high yield embedded systems: reconfigurable, interchangeable and redundant components, a communication network, parallelism, and the tools to use this new kind of architecture. However, what is missing are new methods that exploit these features for better reliability, as current work has only focused on the flexibility aspects of CGRCs. Our work will close this gap with methods that produce high yield and highly reliable embedded systems.
In this project, we will devise methods to develop and implement a multi-functional, self-adaptive coarse-grained reconfigurable core as a reliability enhancer. In the first phase, we developed methods for dynamic remapping in the CGRC to compensate failing processing elements, and use the CGRC for dynamic functional verification, as an assertion processor, and as a drop-in replacement for failed cores.